A clock manager circuit or clock phase shifter can form part of a delay lock loop (DLL) or a digital frequency synthesizer (DFS), for example. DLLs and DFSes are commonly used in programmable logic circuits (PLDs), such as Field Programmable Gate Arrays (FPGAs). They may also be used in other devices such as Application Specific Integrated Circuits (ASICs) or processors that include or can be programmed to include multiple modules or nodes requiring clocks of different phases, all synchronized to a common clock frequency.
Previous versions of clock manager circuits create clock signals having fixed phases relative to a reference clock oscillator. The clock signals are typically multiplexed to allow selection of a desired phase. Since the phases are otherwise not usually configurable, granularity in the available phases is created. The granularity is created since the clock signal outputs available allow selection of staggered phase shifts in steps on the order of only ¼ or ⅛ of the reference clock oscillator-frequency.
FIG. 1 shows components of a clock manager, or clock phase shifter circuit. The circuit initially includes delay blocks 21-25 that receive a common clock signal input (CLK). The delay blocks can be made up of tap coupled delay (TCD) devices with delay components such as delay lines or inverters connected in series and tap outputs provided at different points along the series connections. Additionally or alternatively, the delay blocks 21-25 can be made up of counter controlled delay devices (CCDs) that include a counter clocked by the input clock with overflow of the counter providing the delay output, with the count overflow point set to control the desired phase shift from the input clock. Programmable frequencies in the past have been created by placing the delay block, including either a TCD or CCD, inside a larger loop that runs at the desired output frequency. Prior counter controlled delay line architectures typically involved placing each CCD in series to achieve less granularity. The maximum operation frequency was then limited by the intrinsic delay of the delay block and any other blocks in the loop or series connection.
Five delay blocks 21-25 are shown in FIG. 1. The first four 21-24 provide output signals with phase shifts at ¼ intervals of the phase of the input clock CLK, the phases being labeled p0, p25, p50 and p75 to indicate the intervals. The final delay block 25 provides a 360 degree phase shift from the first block 21. The outputs of the first and last delay blocks 21 and 25 are connected to phase detector 4 to provide a synchronization signal (Sync Signal) for phase synchronization.
The outputs of the delay blocks 21-24 that provide ¼ phase intervals from the input clock CLK are then provided to an output generator 6. The output generator 6 uses the clock outputs from blocks 21-24 to provide the four fixed phase shifted outputs of the clock manager circuit (Output Clocks) each with a 50% duty cycle. For example, signal p25 creates the rising edge and signal p75 creates the falling edge for a 90 degree phase shifted output.
It would be desirable to have a clock manager circuit with less granularity, particularly in a device like an FPGA that can be programmed to include multiple modules, each using a different phase of a common clock. It would further be desirable to provide less granularity without placing additional limits on the maximum output frequency.